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? xicor, inc. 1994, 1997patents pending 7008-1.2 8/26/97 t2/c0/d0 sh 1 characteristics subject to change without notice 16k/64k/128k mps tm eeprom port saver eeprom features ?up to 10mhz data transfer rate ?25ns read access time ?direct interface to mi croprocessors and microcontrollers ?eliminates i/o port requirements ? no interface glue logic required ?eliminates need for parallel to serial converters ?low power cmos ?1.8v?3.6v, 2.5v?5.5v and 5v 10% versions ?standby current less than 1 a ? active current less than 1ma ?byte or page write capable ? 32 - byte page write mode ?typical nonvolatile write cycle time: 2ms ?high reliability ? 100,000 endurance cycles ?guaranteed data retention: 100 years description the port saver memories need no serial ports or special hardware and connect to the processor memory bus. replacing bytewide data memory, the port saver uses bytewide memory control functions, takes a fr action of the board space and consumes much less power. replacing serial memories, the port saver provides all the serial benefits, such as low cost, low power, l ow volt age, and small package size while releasing i/os for more important uses . the port saver memory outputs data within 25ns of an active read signal. this is less than the read acce ss time of most hosts and provides ?no-wait- state? operation. this prevents bottlenecks on the bus. with rates t o 10 mhz, the port saver supplies data faster than required by most host read cycle specifications. this elim inates the need for software nops. the port saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. this ?bit serial? interface allows the port saver to work well in 8-bit, 16 bit, 32-bit, and 64 -bit systems. a write protect (wp) pin prevents inadvertent write s to the memory. xicor eeproms are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. bloc k diagram ce i/o h.v. generation timing & control eeprom command decode and control logic x dec y decode data register wp 7008 frm f02.1 oe we array 16k x 8 p0/cs p1/clk p2/di p3/do system connection internal block diagram p c ports 8k x 8 2k x 8 saved dsp asic a15 a0 d7 d0 oe we mps risc x84161/641/129 this x84161/641/129 device has been acquired by ic microsystems from xicor, inc. ic mic ic microsystems tm
x84161/641/129 2 pin descriptions chip enable ( ce ) the chip enab le input m ust be lo w to enab le all read/ wr ite oper ations . when ce is high, the chip is dese- lected, the i/o pin is in the high impedance state , and unless a non v olatile wr ite oper ation is underw a y , the de vice is in the standb y po w er mode . output enable ( oe ) the output enab le input m ust be lo w to enab le the out- put b uff er and to read data from the de vice on the i/o line . write enable ( we ) the wr ite enab le input m ust be lo w to wr ite either data or command sequences to the de vice . data in/data out (i/o) data and command sequences are ser ially wr itten to or ser ially read from the de vice through the i/o pin. write protect ( wp ) when the wr ite protect input is lo w , non v olatile wr ites to the de vice are disab led. when wp is high, all func- tions , including non v olatile wr ites , oper ate nor mally . if a non v olatile wr ite cycle is in prog ress , wp going lo w will ha v e no eff ect on the cycle already underw a y , b ut will inhibit an y additional non v olatile wr ite cycles . pin configurations: drawings are to the same scale, actual package sizes are shown in inches: v cc nc oe we ce i/o wp v ss 1 2 3 4 8 7 6 5 8-lead soic 7008 frm f01 1 2 3 4 5 6 7 8 14 13 12 11 10 9 14-lead soic ce i/o nc nc nc wp v ss v cc nc nc nc nc oe we pin names 7008 frm t01 i/o data input/output ce chip enable input oe output enable input we write enable input wp write protect input v cc supply voltage v ss ground nc no connect package selection guide 7008 frm t0a 84161 8-lead pdip 8-lead soic 8-lead tssop 84641 8-lead pdip 8-lead soic 20-lead tssop 84129 8-lead pdip 14-lead soic 28-lead tssop 1 2 3 4 5 6 7 20 19 18 17 16 15 14 20-lead tssop ce i/o nc nc nc wp v ss v cc nc nc nc nc oe we 8 9 10 13 12 11 nc nc nc nc nc nc 1 2 3 4 5 6 7 20 19 18 17 16 15 28-lead tssop nc nc wp v ss nc nc nc oe we nc nc 8 9 10 i/o ce nc v cc nc nc ce ce nc nc nc nc nc nc 11 12 13 14 21 22 23 24 25 26 27 28 x84161 x84641 x84129 .190 in. .230 in. .230 in. .390 in. .250 in. .394 in. .252 in. . 252 in. x84129 x84641 nc nc nc oe nc v cc ce i/o 1 2 3 4 8 7 6 5 8-lead tssop x84161 .114 in. .252 in. we wp v ss 8-lead pdip
x84161/641/129 3 device operation the x84161/641/129 are ser ial eepr oms designed to interf ace directly with most microprocessor b uses . stan- dard ce , oe , and we signals control the read and wr ite oper ations , and a single l/o line is used to send and receiv e data and commands ser ially . data timing data input on the l/o line is latched on the r ising edge of either we or ce , whiche v er occurs rst. data output on the l/o line is activ e whene v er both oe and ce are lo w . care should be tak en to ensure that we and oe are ne v er both lo w while ce is lo w . read sequence a read sequence consists of sending a 16-bit address f ollo w ed b y the reading of data ser ially . the address is wr itten b y issuing 16 separ ate wr ite cycles ( we and ce lo w , oe high) to the par t without a read cycle betw een the wr ite cycles . the address is sent ser ially , most signi - cant bit rst, o v er the i/o line . note that this sequence is fully static , with no special timing restr ictions , and the pro- cessor is free to perf or m other tasks on the b us when- e v er the de vice ce pin is high. once the 16 address bits are sent, a b yte of data can be read on the i/o line b y issuing 8 separ ate read cycles ( oe and ce lo w , we high). at this point, wr iting a ? will ter minate the read sequence and enter the lo w po w er standb y state , other- wise the de vice will a w ait fur ther reads in the sequential read mode . sequential read the b yte address is automatically incremented to the ne xt higher address after each b yte of data is read. the data stored in the memor y at the ne xt address can be read sequentially b y contin uing to issue read cycles . when the highest address in the arr a y is reached, the address counter rolls o v er to address $0000 and reading ma y be contin ued inde nitely . reset sequence the reset sequence resets the de vice and sets an inter- nal wr ite enab le latch. a reset sequence can be sent at an y time b y perf or ming a read/wr ite ??read oper ation (see figs . 1 and 2). this breaks the m ultiple read or wr ite cycle sequences that are nor mally used to read from or wr ite to the par t. the reset sequence can be used at an y time to interr upt or end a sequential read or page load. as soon as the wr ite ? cycle is complete , the par t is reset (unless a non v olatile wr ite cycle is in prog ress). the second read cycle in this sequence , and an y fur ther read cycles , will read a high on the l/o pin until a v alid read sequence (which includes the address) is issued. the reset sequence m ust be issued at the beginning of both read and wr ite sequences to be sure the de vice initiates these oper ations proper ly . figure 1. read sequence ce oe we i/o (in) "0" reset when accessing: x84161 array: a15?11=0 x84641 array: a15?13=0 x84129 array: a15?14=0 load address read data a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i/o (out) 7008 frm f04.1 d7 d6 d5 d4 d3 d2 d1 d0
x84161/641/129 4 write sequence a non v olatile wr ite sequence consists of sending a reset sequence , a 16-bit address , up to 32 b ytes of data, and then a special ?tar t non v olatile wr ite cycle command sequence . the reset sequence is issued rst (as descr ibed in the reset sequence section) to set an inter nal wr ite enab le latch. the address is wr itten ser ially b y issuing 16 separ ate wr ite cycles ( we and ce lo w , oe high) to the par t without an y read cycles betw een the wr ites . the address is sent ser ially , most signi cant bit rst, on the l/o pin. up to 32 b ytes of data are wr itten b y issuing a m ultiple of 8 wr ite cycles . again, no read cycles are allo w ed betw een wr ites . the non v olatile wr ite cycle is initiated b y issuing a special read/wr ite ??read sequence . the rst read cycle ends the page load, then the wr ite ? f ollo w ed b y a read star ts the non v olatile wr ite cycle . the de vice recogniz es 32- b yte pages (e .g., beginning at addresses xxxxxx00000 f or x84161). when sending data to the par t, attempts to e xceed the upper address of the page will result in the address counter ?r apping-around to the rst address on the page , where data loading can contin ue . f or this reason, sending more than 256 consecutiv e data bits will result in o v erwr iting pre vious data. a non v olatile wr ite cycle will not star t if a par tial or incom- plete wr ite sequence is issued. the inter nal wr ite enab le latch is reset when the non v olatile wr ite cycle is com- pleted and after an in v alid wr ite to pre v ent inadv er tent wr ites . note that this sequence is fully static , with no spe- cial timing restr ictions . the processor is free to perf or m other tasks on the b us whene v er the chip enab le pin ( ce ) is high. nonvolatile write status the status of a non v olatile wr ite cycle can be deter mined at an y time b y simply reading the state of the l/o pin on the de vice . this pin is read when oe and ce are lo w and we is high. dur ing a non v olatile wr ite cycle the l/o pin is lo w . when the non v olatile wr ite cycle is complete , the l/o pin goes high. a reset sequence can also be issued dur ing a non v olatile wr ite cycle with the same result: i/o is lo w as long as a non v olatile wr ite cycle is in prog ress , and l/o is high when the non v olatile wr ite cycle is done . figure 2: write sequence ce oe we i/o (in) "0" "0" "1" reset load address load data start nonvolatile write a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o (out) 7008 frm f05.1 when accessing: x84161 array: a15?11=0 x84641 array: a15?13=0 x84129 array: a15?14=0 a15 a14 a13 a12 a11 a10 a9
x84161/641/129 5 low power operation the de vice enters an idle state , which dr a ws minimal cur- rent when: ?n illegal sequence is entered. the f ollo wing are the more common illegal sequences: read/wr ite/wr ite?n y time read/wr ite ?when wr iting the address or wr iting data. wr ite ?when reading data read/read/wr ite ?after data is wr itten to de vice , b ut bef ore enter ing the nv wr ite sequence . ?he de vice po w ers-up; ? non v olatile wr ite oper ation completes . while a sequential read is in prog ress , the de vice remains in an activ e state . this state dr a ws more current than the idle state , b ut not as m uch as dur ing a read itself . t o go bac k to the lo w est po w er condition, an in v alid condition is created b y wr iting a ? after the last bit of a read oper ation. write protection the f ollo wing circuitr y has been included to pre v ent inadv er tent non v olatile wr ites: ?he inter nal wr ite enab le latch is reset upon po w er-up . ? reset sequence m ust be issued to set the inter nal wr ite enab le latch bef ore star ting a wr ite sequence . ? special ?tar t non v olatile wr ite command sequence is required to star t a non v olatile wr ite cycle . ?he inter nal wr ite enab le latch is reset automatically at the end of a non v olatile wr ite cycle . ?he inter nal wr ite enab le latch is reset and remains reset as long as the wp pin is lo w , which b loc ks all non v olatile wr ite cycles . ?he inter nal wr ite enab le latch resets on an in v alid wr ite oper ation. symbol table w a veform inputs outputs must be steady will be steady ma y change from lo w to high will change from lo w to high ma y change from high to lo w will change from high to lo w don? care: changes allo w ed changing: state not kno wn n/a center line is high impedance
x84161/641/129 6 absolute maximum ratings* t emper ature under bias ...................... ?5 c to +135 c stor age t emper ature ........................... ?5 c to +150 c t er minal v oltage with respect to v ss ....................................... ?v to +7v dc output current ................................................... 5ma lead t emper ature (solder ing, 10 seconds) .......... 300 c recommended operating conditions 7008 frm t02 *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those indicated in the oper ational sections of this speci- cation is not implied. exposure to absolute maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . 7008 frm t03 temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c military? ?5 c +125 c supply voltage limits x84161/641/129 5v 10% x84161/641/129 ?2.5 2.5v to 5.5v x84161/641/129 ?1.8 1.8v to 3.6v d.c. operating characteristics (v cc = 5v 10%) (ov er the recommended oper ating conditions , unless otherwise speci ed.) 7008 frm t04.2 notes: (1) v il min. and v ih max. are f or ref erence only and are not tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma oe = v il , we = v ih , i/o = open, ce cloc king @ 10mhz i cc2 v cc supply current (write) 2 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 1 m a ce = v cc , other inputs = v cc or v ss i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage v cc ?0.8 v i oh = ?ma notes: ? contact f actor y f or militar y a v ailability
x84161/641/129 7 d.c. operating characteristics (v cc = 2.5v to 5.5v) (ov er the recommended oper ating conditions , unless otherwise speci ed.) 7008 frm t05.1 d.c. operating characteristics (v cc = 1.8v to 3.6v) (ov er the recommended oper ating conditions , unless otherwise speci ed.) 7008 frm t05.1 notes: (1) v il min. and v ih max. are f or ref erence only and are not tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 500 m a oe = v il , we = v ih , i/o = open, ce clocking @ 5mhz i cc2 v cc supply current (write) 2 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 1 m a ce = v cc , other inputs = v cc or v ss i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 1ma, v cc = 3v v oh output high voltage v cc ?0.4 v i oh = ?00 m a, v cc = 3v symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 300 m a oe = v il , we = v ih , i/o = open, ce clocking @ 3mhz i cc2 v cc supply current (write) 1 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 1 m a ce = v cc , other inputs = v cc or v ss i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 0.5ma, v cc = 2v v oh output high voltage v cc ?0.2 v i oh = ?50 m a, v cc = 2v
x84161/641/129 8 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7008 frm t06 notes: (2) p er iodically sampled, b ut not 100% tested. power-up timing 7008 frm t07 notes: (3) time dela ys required from the time the v cc is stab le until the speci c oper ation can be initiated. p er iodically sampled, b ut not 100% tested. a.c. conditions of test 7008 frm t08 equivalent a.c. load circuits symbol parameter max. units test conditions c i/o (2) input/output capacitance 8 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v symbol parameter max. units t pur (3) power-up to read operation 2 ms t puw (3) power-up to write operation 5 ms input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 5ns input and output timing levels v cc x 0.5 5v 30pf 2.06k w 3.03k w output 7008 frm f06 3v 30pf 2.39k w 4.58k w output 7008 frm f07 2v 30pf 2.8k w 5.6k w output
x84161/641/129 9 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle limits ?x84161/641/129 ? notes: (4) p er iodically sampled, b ut not 100% tested. t hz and t ohz are measured from the point where ce or oe goes high (whiche v er occurs rst) to the time when i/o is no longer being dr iv en into a 5pf load. ? contact f actor y f or 10mhz x84129 a v ailabilityread cycle symbol parameter v cc = 5v 10% v cc = 2.5v ?5.5v v cc = 1.8v ?3.6v units min. max min. max. min. max. t rc read cycle time 100 200 330 ns t ce ce access time 25 50 70 ns t oe oe access time 25 50 70 ns t oe l oe pulse width 50 60 90 ns t oe h oe high recovery time 50 60 90 ns t low ce low time 50 70 90 ns t high ce high time 50 120 180 ns t lz (4) ce low to output in low z 0 0 0 ns t hz (4) ce high to output in high z 0 25 0 30 0 35 ns t olz (4) oe low to output in low z 0 0 0 ns t ohz (4) oe high to output in high z 0 25 0 30 0 35 ns t oh output hold from ce or oe high 0 0 0 ns t wes we high setup time 25 25 25 ns t weh we high hold time 25 25 25 ns ce we t wes oe 7008 frm f08 t high t ce t oe t olz t oh t weh high z data t ohz t hz t lz t low t rc i/o oel t t oeh
x84161/641/129 10 write cycle limits ?x84161/641/129 7008 frm t10 notes: (5) t nvwc is the time from the f alling edge of oe or ce (whiche v er occurs last) of the second read cycle in the ?tar t non v olatile wr ite cycle sequence until the self-timed, inter nal non v olatile wr ite cycle is completed. (6) data is latched into the x84161/641/129 on the r ising edge of ce or we , whiche v er occurs rst. (7) p er iodically sampled, b ut not 100% tested. symbol parameter v cc = 5v 10% v cc = 2.5v ?5.5v v cc = 1.8v ?3.6v units min. max. min. max. min. max. t nvwc (5) nonvolatile write cycle time 5 5 5 ms t wc write cycle time 100 200 330 ns t wp we pulse width 25 40 70 ns t wph we high recovery time 65 150 200 ns t cs write setup time 0 0 0 ns t ch write hold time 0 0 0 ns t cp ce pulse width 25 40 70 ns t cph ce high recovery time 65 150 200 ns t oes oe high setup time 25 25 50 ns t oeh oe high hold time 25 25 50 ns t ds (6) data setup time 12 20 30 ns t dh (6) data hold time 5 5 5 ns t wpsu (7) wp high setup 100 100 150 ns t wphd (7) wp high hold 100 100 150 ns
x84161/641/129 11 ce controlled write cycle we controlled write cycle ce oe t wph we 7008 frm f09 wp i/o t oes t cph t oeh t ch t wphd high z data t ds t dh t cp t wp t wpsu t cs t wc ce oe t wph we 7008 frm f10 wp i/o t oes t cph t ch t oeh t wphd high z data t ds t dh t cp t wp t wpsu t cs t wc
x84161/641/129 12 no te: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.1 10 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref . pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 sea ting plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic du al in-line p a cka ge type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62)
x84161/641/129 13 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 3926 frm f22.1 8-lead plastic small outline gull wing p ackage type s 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint note: all dimensions in inches (in parentheses in millimeters)
x84161/641/129 14 packaging information 3926 frm f26 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gull wing p a cka ge type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" t ypical 0.050" t ypical 0.030" t ypical 14 places foo tprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45
x84161/641/129 15 packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop , package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x84161/641/129 16 packaging information note: all dimensions in inches (in p arentheses in millimeters) 20-lead plastic, tssop p ackage type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .300 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 3926 frm f45 see detail ? .031 (.80) .041 (1.05) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x84161/641/129 17 packaging information note: all dimensions in inches (in p arentheses in millimeters) 28-lead plastic, tssop p ackage type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .394 (10.0) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 3926 frm f45 see detail ? .031 (.80) .041 (1.05) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x84161/641/129 18 ordering information *part mark conven tion device x84161/641/129 x x temperature range blank = commercial = 0 c to +70 c i = industrial = ?40 c to +85 c military = ?55 c to +125 c (contact factory) limited warranty devices sold by xicor, inc. are covered by the warr anty and patent indemnification provisions appearin g in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by descri ption regarding the information set forth herein or regarding the freedom of the described devices fro m patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xico r, inc. reserves the right to discontinue productio n and change specifications and prices at any time an d without notice. xicor, inc. assumes no responsibility for the use o f any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the follo wing u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,5 33,846; 4,599,706; 4,617,652; 4,668,932; 4,752, 912; 4,829, 482; 4,874, 967; 4,883, 976. foreig n patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this pro duct should design the system with appropriate error detection and correction, redunda ncy and back-up features to prevent such an occuren ce. xicor's products are not authorized for use in crit ical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical impla nt into the body, or (b) support or sustain life, and whose failure to perfor m, when properly used in accordance with instructio ns for use provided in the labeling, can be reasona bly expected to result in a significant injury to the user. 2.a critical component is any component of a life s upport device or system whose failure to pe rform can be reasonably expected to cause the failu re of the life support device or system, or to affect its safety or effectiveness. g - x v cc range blank = 4.5v to 5.5v, 10 mhz 2.5 = 2.5v to 5.5v, 5 mhz 1.8 = 1.8v to 3.6v, 3 mhz packages: x84161 p = 8-lead pdip s8 = 8-lead soic v8 = 8 -lead tssop x84641 p = 8-lead pdip s8 = 8-lead soic v20 = 20 -lead tssop x84129 p = 8-lead pdip s14 = 14-lead soic v28 = 28 -lead tssop 8 - lead tssop ag = 1.8 to 3.6v, 0 to +70 c eyww 8161xxg ah = 1.8 to 3.6v, -40 to +85 c f = 2.5 to 5.5v, 0 to +70 c g = 2.5 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c 8 - lead soic/pdip x84641 x g xx blank = 8-lead soic ag = 1.8 to 3.6v, 0 to +70 c ah = 1.8 to 3.6v, -40 to +85 c f = 2.5 to 5.5v, 0 to +70 c g = 2.5 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c p = 8-lead pdip g = rohs compliant lead free *all parts and package types not included will receive standard marking. g = rohs compliant lead free g = roh s compliant lead - free package blank = standard package. non lead-free

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